Integrated memory may be configured as an array of memory cells. Each memory cell may include an access transistor in combination with a programmable device. For instance, an example memory cell may comprise an access transistor in combination with a capacitor (a so-called 1T1C memory cell), may comprise two access transistors in combination with a capacitor (a so-called 2T1C memory cell), etc.
In some applications, the access transistors may be vertical devices, and may comprise a channel region vertically between a pair of source/drain regions. Such vertical devices may advantageously occupy a smaller footprint as compared to other configurations (e.g., planar transistor devices), which may enable tighter packing and higher levels of integration. Floating body effects may problematically occur with vertical access transistors; as described in U.S. Pat. No. 8,878,271, with Kamal M. Karda as the first inventor, and which is assigned to Micron Technology, Inc. The floating body effects result from the channel region of a vertical access transistor being within a body of semiconductor material which is not electrically coupled with a reference voltage (i.e., which “floats” rather than being set to a specific reference voltage). The floating body effects may lead to degraded charge retention, power distribution problems, and/or other problems across a memory array.
It would be desirable to develop architectures which alleviate floating body effects associated with vertical access devices, and to develop methods for fabricating such architectures.